As per the International Technology Roadmap for Semiconductors (ITRS) each lower node is 0.7 times the previous technology making chip faster by 17% every year. Scaling down of CMOS technologies to 22nm has significant challenges in design. By reducing the dimensions many challenges like gate leakage, short channel effect (SCE), low voltage operation & delay comes into picture. Thus paper presents the past work done in design of nanoscale MOSFETs. The multi gate MOSFETs structure is considered as important candidates for CMOS scaling to reduce short channel effect. Gate All Around (GAA) & Double Gate (DG) are another design used to reduce SCE & suitable for low voltage operation. Use of Silicon on Insulator (SOI) for the thin short channel, Lower parasitic capacitance, Resistance to Latchup & has 10-20% higher switching speed. This paper shows the various challenges in design of MOSFET & various methods or techniques for increasing the performance of MOSFET at lower node
Loading....